Microprocessors

The 5k86 is AMDs 5th generation x86 implementation, introduced in March 1996. The processor, later renamed to K5, was eagerly awaited and it was hoped that it would provide a viable alternative to the Pentium early in the Pentiums life cycle. Unfortunately, AMD delivered the processor over a year late and at much lower clock speeds than had been originally anticipated. As a result instead of being the Pentium killer AMD had hoped for, the K5 was positioned as a low-cost Pentium alternative.
The K5 is, internally, a very advanced processor, the most advanced of the fifth-generation chips. Internally it is more comparable to the Pentium Pro. It is an x86 translation/emulation processor, decoding x86 instructions into RISC-like microinstructions and executing them on a 6-pipeline internal core. This allows the K5 to achieve higher performance than a Pentium of the same speed.

AMD started in the x86 business as a second-source manufacturer for Intels chip designs. IBM demanded all suppliers have a second manufacturing source, and Intel had to license another company to secure the IBM PC contract. The AMD 80286 was a result of this contract.

The AMD 80286 was in reality Intel-designed all the way, pin and instruction compatible, based upon Intels microcode.

AMDs business in the 1970s was not the creation of new products; it concentrated on making higher quality versions of existing products under license. For example, all of its products met MILSPEC requirements no matter what the end market was. In 1975, AMD began selling reverse-engineered clones of the Intel 8080 processor.

The AMD 9080A was a plug-in replacement for Intels 8080, an unauthorized second source. As a result of that AMD negotiated a technology cross-license and patent cross-license with Intel in 1975 and renamed the chip 8080A.

The Am386 CPU was released by AMD in 1991. A 100%-compatible clone of the Intel 80386 design, it sold millions of units and positioned AMD as a legitimate competitor to Intel, rather than just a second source for Intels x86 CPUs.

While the CPU was essentially ready to be released prior to 1991, Intel kept it tied up in court. AMD had previously been a second-source manufacturer of Intels designs, and AMDs interpretation of the contract was that it covered all of them. Intel, however, claimed that the contract only covered the 80286 and prior processors. After a few years in the courtrooms, AMD finally won the case and the right to sell their Am386. This paved the way for competition in the CPU market and thus lowered the cost of owning a PC.

In 1991 AMD introduced advanced versions of the 386SX processor - not a second source production of the Intel chip, but a reverse engineered pin compatible version. In fact, it was AMDs entry in the x86 market other than as a second source for Intel. AMD 386SX processors were available at faster clock speeds at the time they were introduced and still cheaper than the Intel 386SX.
Produced in 0.8 mm technology and using a static core their clock speed could be dropped down to 0 MHz, consuming just some mWatts. Power consumption was up to 35% lower than with Intels design and even lower than the 386SLs, making the AMD 386SX the ideal chip for both desktop and mobile computers. The SXL versions featured advanced power management functions and used even less power

The Am486 is a 80486-class processors produced by AMD in the 1990s. Intel beat AMD to market by nearly four years, but AMD priced its 40 MHz 486 at or below Intels price for a 33 MHz chip, offering about 20% better performance for the same price. Early AMD 486 chips were drop-in replacements for their Intel counterparts, but later AMD clock-doubled 486s ran at 3.3 volts instead of Intels 5 volts, which limited their suitability as upgrade chips until third-party voltage adapters appeared on the market.

While the Am386 was primarily used by small computer manufacturers, the Am486DX, DX2, and SX2 chips gained acceptance among larger computer manufactuers, expecially Acer and Compaq, in the 1994 time frame.

AMDs higher clocked 486 chips provided superior performance to many of the early Pentium chips, especially the 60 and 66 MHz launch products. While equivalent Intel 80486DX4 chips were priced high and required a minor socket modification, AMD priced low. Intels DX4 chips had twice the cache of the AMD chips, giving them a slight performance edge, but AMDs DX4-100 usually cost less than Intels DX2-66.

Introduced in November 1995, the AMD 5x86 is a standard 486 processor with an internally-set multiplier of 4, allowing it to run at 133 MHz on systems without official support for clock-multiplied DX2 or DX4 486 processors. Like most of the later 486 parts, the 5x86 featured write-back L1 cache, and unlike all but a few, a generous 16 kilobytes rather than the more common 8KB.

Since having a clock multiplier of four was not part of the original Socket 3 design, AMD made the 5x86 look for a two times setting from the motherboard and interpret that as four times instead. In other words, to use the 5x86 you want to set the motherboard to the 2x setting. This will actually cause the 5x86 to run at 4x.

The combination of best-in-class clock speed and the write-back cache allowed the 5x86 to equal or slightly surpass an Intel Pentium 75 MHz processor in business application performance. Also, because it was based on a pure 486 design, it was compatible with older systems, something its slightly faster rival, the Cyrix 5x86, had trouble with.

The Athlon made its debut on August 21, 1999. The original Athlon core revision, codenamed K7, was available in speeds of 500 to 650 MHz at its introduction and was later sold at speeds up to 1000 MHz.

Internally, the Athlon was essentially a major reworking of the K6 processor core designed for compatibility with the EV6 bus protocol (first used on DECs Alpha 21264 RISC processor). AMD dramatically improved the floating-point unit from the K6 and put a large 128K level 1 cache on the chip. Like on the Intel Pentium II there was 512k of secondary cache, mounted on the CPU module and running at a lower speed than the core.
The resulting processor was the fastest x86 in the world. Various different versions of the Athlon held this distinction continuously from August 1999 until January 2002.

The AMD Duron was released in the summer of 2000 as a low-cost alternative to the Athlon processor and the Pentium III and Celeron processor lines from Intel.

The Duron is pin-compatible with the Athlon and operating on the same motherboards. It has the same 128K of level 1 cache as the Athlon, but only 64K of level 2 cache, as compared to 256K on the more expensive chip. Because of this, the Duron generally lags behind the Athlon on business applications, but keeps up in floating-point operations thanks to its powerful FPU, which is identical to the Athlons. The original Duron was limited to operating on a 100 MHz front-side bus speed, while the Athlon at the time could run on a bus clock of 133 MHz. Later Athlons supported a 200MHz bus.

The K5 was developed by AMD to compete with Intels Pentium microprocessor range. Introduced in 1996 almost 2 years late, AMDs problems were compounded by being unable to manufacture the chip at the clock speeds originally projected. In its favor, the K5 did at least offer good x86 compatibility. All models had 4.3 million transistors on-chip. No K5 supported MMX instructions. Internally ambitious, it was closer to a Pentium Pro than a Pentium, based upon an internal highly parallel RISC processor architecture with an x86 decoding front-end.

Improvements and differences to the Intel Pentium include:
Five integer units, which could process instructions out of order, one floating point unit, compared to two units of the Pentium
The branch target buffer was four times the size of the Pentiums, although not reportedly more accurate
Register renaming improved parallel performance of the pipelines
Speculative execution of instructions reduced pipeline stall
The instruction cache is 16 Kb, double the Pentium
The primary cache is 4-way set associative instead of the Pentiums 2-way
The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation was weak. The low clock rates were due in part to AMDs deficiencies as a manufacturing company in the period. However, having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance, is an example of how the actual implementation fell short of the project goals. Additionally, while the K5s floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed. Overall, the chip failed to deliver, both in terms of raw performance, and financially for AMD.

After AMDs plans with the K5 turned into a debacle, AMD again claimed that they had the solution to make them more than just discount alternatives to Intel: A chip with the power of a Pentium Pro, with MMX support and intended to fit into a standard socket 7. AMD delivered its much anticipated K6 chip in April of 1997, beating Intels Pentium II to the market by a month.

AMD showed their commitment to establishing themselves in the market when they purchased NexGen in 1996 and with it, the design for the Nx686 processor. NexGen had been intending to market this chip in its own socket, but AMD changed the design to fit the standard socket 7, added MMX support, and renamed it the K6. Despite the name implying a design evolving from the K5, it is in fact a totally different design that was created by the NexGen team and adapted after the AMD purchase.

The K6 was originally launched running at speeds of 166 and 200 MHz in April 1997. It was followed by a 233 MHz version later in the summer of 1997. The release of the 266 MHz version of this chip was not until spring 1998 when AMD were able to move to the 0.25 micron manufacturing process. The final iteration of the K6 design was released in May 1998 running at 300 MHz and continued with the K6-2.

Initially, the AMD K6 processors used Pentium II Rating (PR2) to designate their speed. The PR2 rating was dropped because the rated frequency of the processor was the same as the real frequency. This item was made in the month the K6 was released (week 17/1997 = April 21st - 27th, 1997) and has the initial PR2 marking.

The K6-2 was a significant improvement over the K6. It built upon the K6s processing core, with the addition of 21 new instructions called 3D Now!. These are SIMD (Single Instruction Multiple Data) instructions designed to enhance the 3D geometry capability of the chips floating point unit. This allowed the K6-2 to overcome the handicap of the slow (relative to Intel) CPU which the K6 owned.

The K6-2 also saw the introduction of a 100 MHz front side bus. This was only available to owners of new Super Socket 7 motherboards which also included features such as AGP. All of these features helped to give the K6-2 performance fast enough to be a credible challenger to the dominant Pentium II. Performance of the two chips was broadly similar: the K6-2 tending to be faster for general-purpose computing, the Intel part clearly superior at floating-point tasks. The K6-2 was a very successful chip and provided AMD with the marketing base and the financial stability it would need to introduce the Athlon.

The K6-2 was originally manufactured in speeds of 266 & 300 MHz in May 1998. The 300 MHz chip saw the introduction of the 100 MHz bus over the conventional 66 MHz bus used by the 266 MHz chip. August 1998 a 333 MHz version on a 95 MHz bus has been released and was quickly followed by a 350 MHz version on the 100 MHz bus. November 1998 saw the release of the 366, 380 and 400 MHz versions of the chip. This has been followed by the release of a 450 MHz K6-2 in February 1999 and the 500 MHz version in August 1999.

The K6-2+ is a revised version of the K6-III. Essentially, the K6-2+ is a K6-III with a 128 KB L2 cache made on a new 180nm production process. It was also the first processors to be available with the PowerNow! power saving technology. Essentially, the power savings were achieved with a combination of frequency (through adjusting multipliers) and voltage reduction.

The K6-III was the last and fastest of all Socket 7 processors. It achieved the distinction of being the fastest x86 processor on the market on release, and remained highly competitive for a considerable time afterwards.

In conception, the design was simple: it was a K6-2 with an additional L2 cache. The original K6-2 had a 64 KB primary cache and a much larger amount of motherboard-mounted cache (usually 512 KB or 1 MB but varying depending on the choice of main board). In contrast the competing Intel parts used 32 KB of L1 cache and either 128 KB of full-speed secondary cache integrated into the CPU itself (Celeron) or 512 KB of half-speed cache mounted on a processor daughter board (Pentium II, Pentium III). The K6-III, however, used both methods: it had 64 KB primary cache, a massive 256 KB on-chip, full-speed secondary cache (similar to the Celerons but twice the size), and the variable size motherboard mounted cache on the Socket 7 main board became a tertiary level.

In execution, however, the design was not simple: with 21.4 million transistors, it was a very large chip to manufacture with early 1999 technology, and the K6 core design did not scale well past 500 MHz. Nevertheless, the K6-III 400 sold well, and the K6-III 450 was clearly the fastest x86 chip on the market on introduction, comfortably outperforming AMDs K6-2s and Intels Pentium IIs.

ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments.

The British computer manufacturer Acorn Computers first developed the Acorn RISC Machine architecture (ARM) in the 1980s to use in its personal computers.

Introduced in 1986, the ARM2 is a reimplementation of the ARM1 on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a research project, the ARM2 became the first commercially successful ARM microprocessor.

The ARM2 was designed to work as an embedded controller or a coprocessor or as a stand-alone microprocessor system. The Acorn Archimedes family of personal computers was built using the ARM2 along with a number of fully custom support chips that were also designed by Acorn Computer.

Late in 1992, Acorn launched new budget machines - two more in the A3000 range (A3010 and A3020) and an A4000 which was a business oriented mini-A5000. The principal difference was a reduction of board complexity with Acorn/ARMs first foray into SoC (System-on-Chip) design in which the main components of the ARM chipset (ARM, MEMC, VIDC, IOC) were coupled together in one piece of silicon. As it happens, initial supply problems meant that early machines did not have an ARM250 but instead a mezzanine board containing the individual chips.
An ARM250 is more or less an ARM3 without the cache, so it ought to be detectable by the lack of a cache but the support of SWP, though the mezzanine version may just behave like a marginally faster ARM2 machine. Clocking 12MHz, this SoC delivers around 7 MIPS.

The next iteration of the ARM processor came in the form of the ARM3. Offering a 4KiB unified cache, plus increased clock speeds (usually 25MHz, although some 33MHz parts exist), it was compatible enough for a carrier board to be designed to plug in where an ARM2 used to be, giving an older machine an instant resurrection as something new.

The ARM3 adds the SWP instruction, which is a atomic instruction to swap data between registers and memory and is guaranteed not to be interrupted (unlike the corresponding LDR/STR sequence) so it may be used for system semaphores.

The first machine to use the ARM3 onboard was Acorns A5000 (1991) and the A4 laptop (1992, although the A5000 design is derived from the A4!). Clocking at 25MHz (24MHz for the A4), the machine offers around 13.5 MIPS, which is about what youd expect for the difference in clock speed. The Alpha versions of the A5000 (clocked at 33MHz) offer nearly 18 MIPS. By way of comparison, an Intel 80386DX clocking 25MHz provides 8.5 MIPS, while the higher power (and phenomenally expensive in its day) 80486(any version) generally offered around 20 MIPS at 25MHz.

ARM7 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use.
The ARM7 core family consists of ARM700, ARM710, ARM7DI, ARM710a, ARM720T, ARM740T, ARM710T, ARM7TDMI, ARM7TDMI-S, ARM7EJ-S. The ARM7TDMI and ARM7TDMI-S were the most popular cores of the family.

Since ARM7 cores were released from 1993 to 2001, they are no longer recommended for new IC designs; instead ARM Cortex-M or ARM Cortex-R cores are preferred.

1993 ARM700
1994 ARM710
1994 ARM7DI
1994 ARM7TDMI
1995 ARM710a
1997 ARM710T

The predecessor of the CX-83D87. The Cyrix 387DX was soon replaced by the much more advanced CX-83D87

The Cyrix 486DLC is pin compatible to the Intel i386DX.
While the internals of the 486DLC are roughly equivalent to those in the i486SX, the bus interface is identical to that of the Intel 386DX, respectively to allow easy replacement of the Intel CPUs by the Cyrix chips.
The overall execution speed is about same as with an i486SX, but if you add a matching Cyrix FPU, e.g. a Cyrix 83D87, the speed is about 50% faster than an i486DX running at the same frequency.

The Cyrix Cx486DX was designed to be completely software-compatible with Intels i486DX processor.
It is not just an Intel clone but a completely new design by Cyrix.
Compared to the i486DX the Cx486DX had an improved cache algorithm and therefore was faster in specific applications. The price for a Cx486DX was a little lower than for Intels 486DX and made the processor a very common i486DX alternative.

The 487DLC is a math processor for the Cyrix 486 DLC series of 386DX replacement processors.
The Cx487DLC is an OEM only chip and has not been sold separately.

The 5x86 processor utilizes efficient fifth-generation (Pentium class) architectural features to significantly improve performance while minimizing transistor count. It achieves this performance using a superpipelined architecture in the integer unit combined with data forwarding, branch prediction, a 16-KByte unified write-back cache, single-cycle instruction decode, and single-cycle execution.

The processors built-in power-saving features automatically power down the Floating Point Unit (FPU) and other idle internal circuits, while the System Management Mode (SMM) conserves power flowing to system peripherals.

The Cyrix 5x86 processor is an example of Cyrixs strategy to design next-generation processor architectures that leverage existing designs. It is available in a 168-pin PGA or a 208-pin QFP package with standard 486 pinout. Though its installed in a P24D socket on a 486 motherboard, the motherboard must have a BIOS that will support the 5x86.

The successor to the 6x86 and 6x86L is the 6x86MX (M2), introduced May 30, 1997 and intended to compete with AMDs K6 and Intels Pentium MMX.
The 6x86MX is an evolutionary step from the 6x86 and is very similar to it in internal function.
The 6x86MX supports the MMX extension and also features several other improvements over the original 6x86 chip.
The internal cache was increased from 16 to 64 KB, a 256 byte additional pre-cache was added to help improve efficiency in how the regular level 1 cache is operated, the Branch Prediction was improved and the internals of the chip have been optimized for 32-bit operation.

This 80287-compatible chip was developed from the Cyrix 83D87 and has been available since 1991. It complies completely with the IEEE-754 standard for floating-point arithmetic and features nearly total compatibility with Intels coprocessors, including implementation of the full Intel 80387 instruction set. It implements the transcendental functions with the same degree of accuracy and the superior speed of the Cyrix 83D87. This makes the Cyrix 82S87 the fastest and most accurate 287 compatible coprocessor available.

Documentation by Cyrix rates the 82S87 at 730 kWhets/sec for a 12.5 MHz system, while the Intel 287XL performs only 552 kWhets/sec. 82S87 chips manufactured after 1991 use the internals of the Cyrix 387+, which succeeds the original 83D87.

The CX-83D87 was introduced in 1989. It is the fastest 387-compatible coprocessor and provides up to 50% more performance than the Intel 387DX.
The 83D87 also offers the most accurate transcendental functions of all coprocessors. It is the 387 clone with the highest degree of compatibility to the Intel 387DX.
Unlike the Intel 387DX, the 83D87 (and all other 387-compatible chips as well) does not support asynchronous operation of CPU and coprocessor.
To reduce power consumption the 83D87 features advanced power saving features. Those portions of the coprocessor that are not needed are automatically shut down. If no coprocessor instructions are being executed, all parts except the bus interface unit are shut down.

After Cyrix was purchased by National Semiconductor in 1997 they terminated their foundry agreement with IBM. National fabricated their own chips and the 6x86MX was re-named MII.
Compared to early 6x86MX CPUs the MII had some enhancements to its processor core.
Heat output was reduced allowing it to rise to clock speeds over 220MHz. The MII also required non-standard bus speeds at 75 or 83MHz on socket 7 boards and therefore had some troubles with stability.

In 1996 Cyrix released the MediaGX CPU, which integrated all of the major discrete components of a PC, including memory controller, graphics, sound and PCI controller, onto a single chip. Initially based on the old 5x86 technology and running at 120 or 133 MHz, its performance was widely criticized but its low price made it quite successful. Though it required a special motherboard and was not pin compatible with the Pentium, it was the cheapest route into a Pentium class system available on the market. Later versions of the MediaGX ran at speeds of up to 333 MHz and added MMX support. A second chip was added to extend its video capabilities.

The MediaGX led to Cyrixs first big win, when Compaq used it in its lowest-priced Presario computers. This led to further MediaGX sales to Packard Bell and also seemed to give Cyrix legitimacy, as 6x86 sales to Packard Bell and eMachines quickly followed.

But because it seemed to have so much potential in the low-cost market, it dragged Cyrixs attention away from the main market - high-performance desktop parts - and attracted the interest of other companies, notably National Semiconductor, which bought Cyrix in July 1997 largely on the strength of the MediaGX design, and over the next year or so proceeded to mismanage the company into oblivion.

Cyrix entered the fifth generation processor market with the 6x86 processor, formerly projected as the M1. As a successful and cheaper (often less than half the cost) alternative to the Intel Pentium, it is pin- and voltage-compatible with it. Cyrix gave it the 6x86 name in reference to some of its more advanced features, which it calls sixth generation. In reality, the processor is comparable in power and architecture to the fifth-generation Pentium.

The 6x86 is not a Pentium clone. Clones are exact or near-exact copies, usually being reversed engineered or based on licensed code. The 6x86 is based on an original Cyrix design. It incorporates several advanced architectural features that allow it to outperform a Pentium of equal clock speed. For this reason Cyrix helped invent the P-Rating system. This was an advantage to help people make a valid comparism but also caused some confusion when setting the appropriate clock speed on the motherboard.

The Cyrix 6x86 range has the most powerful processor core of any x86 processor of its generation. Unfortunately, like the AMD K5, it also has a very slow floating point math capability and so was a very poor games and 3D performer.

The processor is designed for Socket 7 and is available in several clock speeds, some of them rather unusual. The 6x86 PR200 (150 Mhz) processor introduced non-standard bus speeds up to 75 MHz - many motherboards and PCI cards did not support this speeds: Since the PCI bus runs at half of the mainboard bus speed, you are increasing the PCI bus to 37.5 MHz with a bus speed of 75 MHz. Several PCI cards, especially some graphics cards, did not run correctly with this overclocked bus.

Nintendo Game Boy, based on Z80

Entex Select-A-Game

The PowerPC 600 family was the first family of PowerPC processors built.
The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620

The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. It was designed to be a low cost, low end processor for portable and embedded use. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four-stage pipeline and five execution units: integer unit, floating point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 75 MHz. The 603 core did not have hardware support for SMP.

A 200 MHz Motorola PowerPC 603 in a ceramic Ball Grid Array packaging.
The PowerPC 603 had 1.6 million transistors and was fabricated by IBM and Motorola in a 0.5 μm CMOS process with four levels of interconnect. The die was 85 mm2 large drawing 3 W at 80 MHz. The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC G3.

The 603 was intended to be used for portable Apple Macintosh computers but could not run 68K emulation software with performance Apple considered adequate, due to the smaller processor caches. As a result, Apple chose to only use the 603 in its low-cost desktop Performa line

The 386 was the successor to the 80286 processor and the first Intel processor with 32-bit data and address busses. It can address four gigabytes (2^32 bytes) of memory - however, 16 megabytes is a typical maximum in IBM PCs. The 386 allows multiple application programs to run at the same time (when running under 386-specific operating systems) using protected mode.

The first IBM compatible to use the 386 was the Compaq 386, before IBM used it in high-end models of their PS/2 series.

With the 386, Intel introduced the DX - SX naming system. DX stands for Double-word eXternal, SX for Single-word eXternal. The SX versions therefore are lower-speed version of the 386(DX). They use a 16-bit data bus instead of a 32-bit data bus.

With the 386, Intel introduced the DX - SX naming system.
DX stands for Double-word eXternal, SX for Single-word eXternal.
The SX versions therefore are lower-speed version of the 386(DX).
They use a 16-bit data bus instead of a 32-bit data bus.

Mathematical coprocessors for the i386SX

The 4004 was the first single chip microprocessor, originally designed and manufactured by Intel for Busicom for use in their calculators. It was invented by Intel engineers Federico Faggin, Ted Hoff, and Stan Mazor and introduced in November 1971.

The Intel 4040 is the successor to the Intel 4004. It was introduced in 1974.
The 4040 added 14 instructions, larger stack (8 level), 8K program space, 8 more registers, and interrupt abilities. It was used primarily in games, instrumentation and point of sale terminals, development- and control equipment. The 4040 family is also referred to as the MCS-40.

The 486 is very similar to its predecessor, the 386. Main differences are an optimised instruction set, an on-chip unified instruction and data cache, an optional on-chip floating-point unit (FPU), and an enhanced bus interface unit. These improvements yield a rough doubling in performance over an 386 at the same clock rate.

There are several suffixes and variants including:
486SX - 486 with its FPU disabled
486DX - 486 with a working FPU
486DX-2 - runs at twice the external clock rate
486SL - 486DX with power conservation circuitry
486SL-NM - 486SX with power conservation circuitry
487 - 486DX with slightly different pinout for use in 486SX systems as FPU
OverDrive - 486DX-2 with slightly different pinout for use in 486SX systems
RapidCAD - 486DX in a special package with a companion FPU dummy package for use in 386 systems
486DLC - mix version by some manufacturers, featuring a 486 instruction set and a 386-compatible pinout
The 486 processor has been licensed or reverse engineered by other companies such as IBM, AMD and Cyrix. Some manufacturers made hybrid 386/486 CPUs (Cxrix Cx486DLC, Texas Instruments TX486DLC), having a 486 instruction set and a 386-compatible pinout.

486DX-2 - runs at twice the external clock rate

Identical in design to 486DX but without a math coprocessor. The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually a 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPUs with only 1 effectively turned on

The first version was an 80486DX with disabled math coprocessor in the chip and different pin configuration. If the user needed math coprocessor capabilities, he must add 487SX which was actually a 486DX with different pin configuration to prevent the user from installing a 486DX instead of 487SX, so with this configuration 486SX+487SX you had 2 identical CPUs with only 1 effectively turned on

The Intel 8008 was an early CPU designed and manufactured by Intel, introduced in April, 1972.

The 80186 microprocessor was developed by Intel in 1982. It is an improved 8086 with several common support functions built in: clock generator, system controller, interrupt controller, DMA controller, and timer/counter. It also added 8 new instructions and executes instructions faster than the 8086. As with the 8086, it has a 16-bit external bus and is also available as the 80188, with an 8-bit external data bus. The initial clock rate of the 80186 and 80188 was 6 MHz. They were, and still are, generally used as embedded processors but also as the CPU of few personal computers:
The Mindset graphics computer, a very advanced computer for the time. It had proprietary chips that enhanced and sped up the graphics.
The original Gateway Handbook, a small subnotebook computer.
The Telenova Compis, a Swedish school computer.
The Tandy 2000, a somewhat PC-compatible workstation featuring particularly advanced graphics for its time.
In 1987 Intel announced the second generation of the 80186 family: the 80C186/C188. The 80186 was redesigned as a static, stand-alone module known as the 80C186 Modular Core and is pin compatible with the 80186 family, while adding an enhanced feature set. The high-performance CHMOS III process allowed the 80C186 to run at twice the clock rate of the NMOS 80186, while consuming less than one-fourth the power.
In 1991 the 80C186 Modular Core family was again extended with the introduction of the 80C186XL. The 80C186XL/C188XL is a higher performance, lower power replacement for the 80C186/C188.

The 80286 was introduced by Intel on February 1, 1982. As the 80186/80188 CPUs were not really significant to personal computing, the 80286 was Intels next step processor for micro computers.

Intel added four more address lines to the 8086/80186 design. The 8086, 8088, 80186, and 80188 all contained 20 address lines, giving these processors one megabyte of addressibility (2^20 = 1MB). The 80286, with its 24 address lines, gives 16 megabytes of addressibility (2^24 = 16 MB).

The most substantial difference between the 80286 and the 8086/8088 is the addition of a protected mode. In protected mode, segment registers became pointers into a table of memory descriptors rather than being a direct part of the address. Among other things, protected mode allows safe execution of multiple programs at once by protecting each program in memory. DOS normally operates in real mode, in which segment registers act just as they do in the 8086/8088. Protected mode is used by Microsoft Windows, IBMs OS/2 and UNIX. (For an introduction to protected mode please refer to this source)

The 80286 is a much more powerful CPU than the 8086, offering 3-6 times the performance of it. The 6 MHz 80286 is the CPU of the IBM AT (Advanced Technology), which also introduced a 16-bit motherboard and 16-bit expansion bus to the PC world. The IBM AT was introduced in 1985 - three years after introduction of the 80286.

With the 80286, the first chipsets were introduced. The computer chipset is a set of chips that replaced dozens of other peripheral chips while maintaining identical functionality. Chips and Technologies became one of the first popular chipset companies.

Intel second-sourced the 80286 to ensure an adequate supply of chips to the computer industry. AMD, IBM, and Harris were known to produce 80286 chips as OEM products; while Siemens, Fujitsu, and Kruger either cloned it or were also second-sources. Between these various manufacturers, the 80286 was offered in speeds ranging from 6 MHz to 25 MHz:

Intel: 6 - 12.5 MHz
Siemens: 8 - 16 MHz
AMD: 8 - 20 MHz
Harris: 10 - 25 MHz

The 80286 was typically made in 3 package versions, each with 68 contacts: a PGA-, CLCC- and a PLCC-package.

Its successor is the 386.

The 286 was widely used in IBM PC compatible computers during the mid to late 1980s.

Mathematical coprocessors for the 80286

The Intel 8080 is an early 8-bit CPU, released in April 1974 running at 2 MHz, and is generally considered to be the first truly usable microprocessor CPU design. It is the successor to the Intel 8008, with which it was assembly language source-compatible because it used the same instruction set developed by Computer Terminal Corporation. The 8080s 40 pin DIP packaging permitted it to provide a 16-bit address bus and an 8-bit data bus, allowing access to 64 kilobytes of memory. It has seven 8-bit registers (six of which could be combined into three 16-bit registers), a 16-bit stack pointer to memory (replacing the 8008s internal stack), and a 16-bit program counter.

The 8080 had 256 I/O ports allowing I/O devices to be connected without the need to allocate memory space - as is required for memory mapped devices - but at the expense of having programmers deal with separate I/O instructions. The first single-board microcomputer was built on the basis of the 8080.

The 8080 was used in many early computers, such as the MITS Altair 8800 and IMSAI 8080, forming the basis for machines running the CP/M operating system (the later, fully compatible and more capable, Zilog Z80 processor would capitalize on this, with Z80 & CP/M becoming the dominant CPU & OS combination of the period much like x86 & MS-DOS for the PC a decade later). Shortly after the launch of the 8080, the Motorola 6800 competing design was introduced, and after that, the MOS Technology 6502 clone of the 6800.

At Intel, the 8080 was followed by the compatible and electrically more elegant 8085, and later by the assembly language compatible 16-bit 8086 and then the 8/16-bit 8088, which was selected by IBM for its new PC to be launched in 1981. The 8080, via its ISA, thus got a lasting impact on computer history.

The 8080 was very popular and was second-sourced by various manufacturers. Clones of the 8080 were also made in former Eastern Block countries like USSR, Poland, CSSR, Hungary and Romania.

The Intel 8085 is an 8-bit processor made by Intel and introduced in 1976. It is binary compatible with the Intel 8080 but requires less supporting hardware, thus allowing simpler and less expensive microcomputer systems to be built.

Intel made the 8085 as a significant improvement on the 8080, both in performance and handling issues. It has improved hardware by only using +5V power (the 8080 required +5V, -5V and +12V), and clock generator and bus controller circuits on-chip. The 5 in the model number came from the fact that the 8085 required only a 5-volt power supply. The 8085 was a transition design on the way to the 16-bit 8086.

There are multiple versions of Intel 8085 processor: The original 8085, the 8085A with bug fixes and the 8085AH HMOS version. Some second-source manufactures also produced CMOS version of the 8085 microprocessor (80C85).

The 8086 is a 16-bit microprocessor chip designed by Intel in 1978 - the introduction to the x86 architecture. Shortly later the 8088 was introduced with an external 8-bit bus, allowing the use of cheap chipsets. It was based on the design of the 8080 with a similar register set, but was expanded to 16 bits.

It featured four 16-bit general registers, which could also be accessed as eight 8-bit registers, and four 16-bit index registers (including the stack pointer).

The processor runs at clock speeds between 4.77 (in the original IBM PC) and 10 MHz.

The 8086 was cloned by the NEC V20, NEC V30 and NEC V50. There are mathematical coprocessors for the 8086, the 8087.

Mathematical coprocessors for the 8086

The Intel 8088 (eighty-eighty-eight, also called iAPX 88) microprocessor is a variant of the Intel 8086.
Introduced on June 1, 1979, the 8088 had an eight-bit external data bus instead of the 16-bit bus of the 8086.
The 16-bit registers and the one megabyte address range were unchanged, however.
In fact, according to the Intel documentation, the 8086 and 8088 have the same execution unit (EU)—only the bus interface unit (BIU) is different.
The original IBM PC was based on the 8088, as were its clones.

The IntelDX4 is a clock-tripled i486 microprocessor with 16 KB L1 cache.
Intel named it DX4 (rather than DX3) as a consequence of litigation with AMD over trademarks.
The product was officially named the IntelDX4, but OEMs continued using the i486 naming convention

The successor to the 486. It has two 32-bit 486-type integer pipelines with dependency checking and can execute a maximum of two instructions per cycle.
It does pipelined floating-point and performs branch prediction. It has 16 kilobytes of on-chip cache, a 64-bit memory interface, 8 32-bit general-purpose registers and 8 80-bit floating-point registers.

Intel called its 586 processor Pentium because a US court ruled that you cant trademark a number.

Intel Pentium 4 is a family of high-performance microprocessors that succeeded Pentium III family.
Pentium 4 CPUs are based on new NetBurst micro-architecture, which differed significantly from P6 micro-architecture used in Pentium II/Pentium III microprocessors.
As an overall CPU performance is proportional to its frequency and its efficiency, to achieve better performance levels many micro-architectures, including P6, strike a delicate balance between faster CPU frequencies and improved efficiency.

The Pentium II is a sixth-generation x86 architecture microprocessor by Intel, introduced on May 7, 1997. It was based on a modifed version of the P6 core first used for the Pentium Pro, but with improved 16-bit performance and the addition of the MMX instructions which had already been introduced on the Pentium MMX.

Unlike previous Intel processors such as the Pentium and Pentium Pro, the Pentium II was packaged in a slot-based form-factor rather than a socket one. This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled bus. This separate cache was slower (running at half the processor speed) than that in the Pentium Pro, but solved the Pentium Pros low yields allowing Intel to introduce the Pentium II at a mainstream price level.

A low-end version of the Pentium II - essentially a Pentium II with less (or no) level 2 cache - was marketed under the name Celeron. The Pentium II Xeon was a high-end version intended for use on servers.

By early 1999, the Pentium III superseded the Pentium II.

The Celeron family is a line of budget x86 processors based on Pentium P6 designs. It is marketed by Intel as a second line to complement their more expensive but higher-performance Pentium CPUs. The first Celeron was introduced in April 1998 and based on the Pentium II. Later versions are based on the Pentium III and Pentium 4 designs.

The Celeron product concept was introduced by Intel in response to the companys loss of low-end market share, in particular to Cyrixs 6x86 and AMDs K6, but also to other competers such as the IDT Winchip. Intels venerable Pentium MMX was no longer performance competitive and although a faster Pentium MMX would be cheap to make and technically straightforward, Intel preferred to move away from the industry standard Socket 7 platform (for which competitors made drop-in replacement CPUs) and produced a budget part that was pin-compatible with their high-end Pentium II product (Slot 1). For both technical and legal reasons, competitors had difficulty making Slot 1 parts.

The Pentium II OverDrive is a processor upgrade designed for Pentium Pro (Socket 8) based systems. By using the 0.25 micron Deschutes core of the Pentium II, Intel managed to put a quick end to the 16-bit weakness of the Pentium Pro, and in doing so, they also managed to double the amount of L1 cache on the processor to 32KB. The PII OverDrive is nothing more than a Pentium II Xeon on a smaller scale, using the Pentium IIs design to place the L2 cache externally off of the CPU, but on a card that would allow it to operate at the same clock speed as the CPU itself. The chip has a built in clock multiplier of 5.0x, and it derives its clock speed based on the motherboards set FSB frequency, so on a 60Mhz board (150/180MHz Pentium Pro systems) the processor operates at 300MHz, on 66MHz systems (166/200MHz Pentium Pro) at 333MHz.

The Pentium II Xeon was introduced in June 1998 as Intels new line of server and workstation processors. The PII Xeon core, manufactured in a .25 micron process, is not much different from the Pentium IIs core. It added multiprocessing support for quad CPU systems and even 8 CPUs in one system and a few enhancements, such as support for more than 4GB of memory. The biggest difference in both performance and architecture comes from the PII Xeon’s L2-cache, at 512KB, 1 or even 2 MB and running at full clockspeed, while the Pentium II was only offered with a 512KB L2 cache running at half CPU clockspeed.

The PII Xeon also introduced Intels biggest processor module so far (about twice the size of a Pentium II cartridge) to include the CPU core and up to four 512KB L2 cache chips.

The Pentium III is an x86 (more precisely, an i686) architecture microprocessor by Intel, introduced on February 26, 1999. Initial versions were very similar to the earlier Pentium II, the most notable difference being the addition of SSE instructions. As with the Pentium II, there was also a low-end Celeron version and a high-end Xeon version. The Pentium III was eventually superseded by the Pentium 4. An improvement on the Pentium III design is the Pentium M.

Second generation Celeron, based on the Pentium III.

The Celeron family is a line of budget x86 processors based on Pentium P6 designs. It is marketed by Intel as a second line to complement their more expensive but higher-performance Pentium CPUs. The first Celeron was introduced in April 1998 and based on the Pentium II. Later versions are based on the Pentium III and Pentium 4 designs.

The Celeron product concept was introduced by Intel in response to the companys loss of low-end market share, in particular to Cyrixs 6x86 and AMDs K6, but also to other competers such as the IDT Winchip. Intels venerable Pentium MMX was no longer performance competitive and although a faster Pentium MMX would be cheap to make and technically straightforward, Intel preferred to move away from the industry standard Socket 7 platform (for which competitors made drop-in replacement CPUs) and produced a budget part that was pin-compatible with their high-end Pentium II product (Slot 1). For both technical and legal reasons, competitors had difficulty making Slot 1 parts.

References: Intel Celeron Processor Home

The second Pentium III version, Coppermine, had an integrated full-speed 256 KB L2 cache with lower latency, which improved performance over Katmai. Under competitive pressure from AMDs Athlon processor, Intel also re-worked the chip internally, and finally fixed the well known instruction pipeline stalls. The result was a remarkable 30% increase in instruction processing performance.

It was built on a 0.18 m process. Pentium III Coppermines running at 500, 533, 550, 600, 650, 667, 700, and 733 MHz were first released on October 25, 1999. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz (1GHz).

A 1.13GHz version was released in mid-2000, but famously recalled after a popular hardware review website proved it was not stable enough to compile the Linux kernel. The problem was traced to the integrated cache, which simply could not operate at speeds above 1GHz. Intel needed at least six months to resolve this problem and released 1.1 and 1.13 GHz versions in 2001.

The third Pentium III-version, Tualatin, was really just a trial for Intels new 0.13 �m process. As the Pentium 4 had a much bigger die size than the Pentium III, Intel would get more usable Pentium IIIs out of a wafer, and this would allow them to introduce the 0.13 �m Pentium 4 (Northwood) once the process was achieving optimal yields. Tualatin performed quite well, especially in variations which had 512 KiB L2 cache (called the Pentium III-S). The Pentium III-S variant was mainly intended for servers, especially those where power consumption mattered, i.e., thin blade servers.

Pentium III Tualatins were released during 2001 until early 2002 at speeds of 1.0, 1.13, 1.2, 1.26, 1.33 and 1.4 GHz. Intel did not want a repeat of the situation where the performance of a lower priced Celeron rivaled that of the more expensive Pentium II, so Tualatin never ran faster than 1.4 GHz, the introductory clock rate of the Pentium 4. Overclockers discovered as well that 1.4-1.5 GHz with air-cooled temperatures was reaching the limits of the process and so Intel may have also wanted to avoid sacrificing profits with lower yields of a faster chip.

The Tualatin core was named after the Tualatin Valley and Tualatin River in the Oregon area. Tualatins can be visually distinguished from Coppermine-based Pentium IIIs by the metal heatspreader fixed on top of the package.

A modified version of Coppermine was developed for Microsofts Xbox game console. The only significant change was that the chip lost half of its L2 cache, dropping it down to 128 KB. Unlike the Celeron Coppermine variant with the same size L2 cache, Xboxs Coppermine core kept all of its 8-way L2 cache associativity from the Pentium III. This meant that the Xbox CPUs L2 cache was more efficient than Celerons. The Xbox CPU was manufactured onto the same Micro-PGA2 packaging as notebook chips.

The Pentium III Xeon was introduced in March 1999. Early versions (Code named Tanner) where built in .25 micron technology and featured a 100MHz front side bus, 512KB to 2MB L2 off-die cache sizes and multiprocessor support for up to 8 CPUs. In October 1999 Intel introduced the 2nd generation PIII Xeon Cascades, using the same core as the .18 micron Pentium III Coppermine processor. As a result the Cascades has its 256KB on-die L2 cache running at full clock speed and all the other Coppermine features like Advanced Transfer Cache, Advanced System Buffering, support for 133 MHz front speed bus, SSE (Streaming SIMD Extensions), etc.

However, the introduction of Cascades had some severe drawbacks: The small 256KB L2 cache took back the Xeons performance advance over the standard Pentium III and the 133MHz bus protocol did not support more than 2 CPUs in a system. In May 2000 Intel finally released a large cache version with up to 2MB (on-die) L2 cache and 100MHz front side bus, again supporting multiprocessing with up to 8 CPUs.

In October 1996 Intel released the 4th Pentium generation as the Pentium with MMX Technology (usually just called Pentium MMX); it was based on the standard Pentium core, the 0.35 �m process of 3rd generation Pentiums was also used for this series, but it had a new set of 57 MMX (MultiMedia eXtensions) instructions to improve working on multimedia tasks, such as encoding and decoding media. However, software must be specially optimized to make use of MMX, and the increased speed the Pentium MMX showed at its apparition was mainly due to the fact that the internal cache had been doubled in size to 32 KB.

With the introduction of the Intel Pentium with MMX Technology, Intel also created OverDrive processors to upgrade existing Pentium motherboards to the new MMX chip. Most older Pentium motherboards cannot handle the new Pentium with MMX because of its requirement for a 2.8V core. Keeping with the tradition of Intels OverDrive line, the Pentium with MMX OverDrive includes a converter that lets it run in Socket 5 motherboards (except for the 200) and Socket 7s that do not have 2.8V support. Otherwise the chip is identical to the standard Pentium with MMX.

This Pentium OverDrives are Intel Pentium processors for 486 Socket 3 and Socket 2 motherboards, provided as a means to give a Pentium performance-level upgrade option for owners of 486 computer systems. It was however criticised for being more expensive and slower than competing CPU-upgrade options such as the AMD Am5x86 and Cyrix 5x86, and being too late to the market. Mainboard compatibility was also a problem, it turned out that many boards didnt support this new chip.

To perform properly, the Pentium OverDrive was dependent on a high amount of secondary cache ram being present on the motherboard; without it the chip was only a trivial amount faster than a DX4.

The Pentium Pro is a sixth-generation x86 architecture microprocessor by Intel originally intended to replace the original Pentium in a full range of applications, but later reduced to a more narrow role as a server and high-end desktop chip. It was introduced using an enormous rectangular Socket 8 form factor in November 1995. Intel has since discontinued it in favor of the newer high-end Xeon processor lines.

Despite the name, the Pentium Pro is actually quite different from Intels earlier Pentium processor, being based on the then-new P6 core (which in a modified form would later be used for the Pentium II, Pentium III and Pentium M). The P6 core features out-of-order execution, speculative execution, and an additional pipe for simple instructions.

Intel called its 586 processor Pentium because a US court ruled that you cant trademark a number.

R3000, the first successful MIPS design in the marketplace with more than 1 million processors made. The R3000 was used in high-end UNIX computers by Siemens and DEC and in the Silicon Graphics SGI Personal IRIS 4D/20 graphic workstations. On this machines 3D sequences for movies like The Abyss, Jurrasic Park or Terminator 2 were rendered.

The R3000 has an interface to handle 3 coprocessors. Each coprocessor has a flag line connected with the CPU that can be tested and a conditional branch executed dependent on its value. Coprocessor instructions can be executed directly from the instruction stream.
Coprocessor 0 (CP0) is incorporated on the CPU chip and supports the virtual memory system and exception handling. It is also referred to as the System Control Coprocessor. CP1 is reserved for the floating point coprocessor. An FPU is mandatory for most R3000 systems. CP2 is available for specific implementations and is often used to accelerate memory access by connecting it to an R3020 memory buffer or an R3220 read/write buffer chip. Later versions of the R3000 (R3000A) had built in memory buffer circuitry.

The MIPS R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture and moved the FPU onto the main die to create a single-chip system.
The design was so important to SGI, at the time MIPS major customer, that SGI bought the company in 1992.
The R4x00 processors have been available and used in different versions.
PC (as in R4000PC) denotes primary cache only and SC denotes secondary cache.
The MC versions contain special support for cache architectures in multiprocessor systems.
R4000 processors where used in many Silicon Graphics computers, e.g. the Indigo workstations and Crimson servers.

The 6502 is an 8-bit processor designed by MOS Technology in 1975, based on the design of the Motorola 6800. When it was introduced it was the least expensive full featured CPU on the market by far, at about 1/6th the price, or less, of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the Zilog Z80, sparked off a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies; it is still made for embedded systems.

Unlike the Intel 8080 and its kind, the 6502 had very few registers. It was an 8-bit processor with 16-bit address bus. Inside was one 8-bit data register (accumulator), two 8-bit index registers and an 8-bit stack pointer. When the 6502 was introduced, RAM was actually faster than CPUs, so it made sense to optimize for RAM access rather than increase the number of registers on a chip.

6502 processors were used in a variety of home computers of the early 80s, for example in:
Commodore PET and VC20
Apple I, II and III
Atari 400, 800, 600/800XL
Acorn Atom and Electron

This CPU is built in my Commodore C64 computer from 1983.

The MOS6510 is a 6502 with an additional 6 Bit bidirectional I/O Port. (The pre-release spec of the 6510 mentions a 8Bit port and since there was never a official release specification of the 6510 all literature copied the version with the 8Bit wide Port. Maybe it was planned, but in the end the 6510 got only an additional 6Bit.)

The 6510 (and the 6502) can run also at 2Mhz. So does the 8502 version in the C128 Computer and the 6502 in the 1571 Disk Drive. The 6510 that was built in the C64 ran at 1 Mhz, so it was compatible to the VIC2 Videochip.

The 7501 variant of the 6510 was used in Commodores C16, C116 and Plus/4 home computers, and the 2 MHz-capable 8502 variant was used in the Commodore C128. All these CPUs are opcode compatible (including undocumented opcodes).

In 1985 MOS produced the 8500, an HMOS version of the 6510. Other than the process change, it is virtually identical to the NMOS version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However in 1985, limited quantities of 8500s were found on older NMOS based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset.

The MOS 8502 was also based on the MOS 6510 that was used in the Commodore 64. The 8502 added the ability to run at a double (2.048 MHz) clock rate, in addition to the standard 1.024 MHz rate used by the Commodore 64. The pinout is a little bit different from the 6510. The 8502 has an extra I/O-pin and lacks the PHI2-pin that the 6510 had.

The 7501/8501 variant of the 6510 was used in Commodores C16, C116 and Plus/4 home computers, and the 2 MHz-capable 8502 variant was used in the Commodore C128. All these CPUs are opcode compatible (including undocumented opcodes).

The 6800 processor was released by Motorola in 1974, shortly after the Intel 8080. It was the basic for Motorolas entrance into the microprocessor market. Like the Intel 8080 it was designed as an enhancement of the Intel 8008 but is not technically based on it

The Motorola 68000 (sixty-eight-thousand; also called the m68k or Motorola 68k, sixty-eight-kay) is a 16/32-bit CISC microprocessor, introduced in 1979 by Motorola Semiconductor Products Sector.

The first member of Motorolas family of 16- and 32-bit processors. Successor to the 6809 and followed by the 68010.

The 68000 has 32-bit registers but only a 16-bit ALU and external data bus. It has 24-bit addressing and a linear address space. Addresses are computed as 32 bit, but the top 8 bits are cut to fit the address bus into a 64-pin package (address and data share a bus in the 40 pin packages of the 8086).

The 68000 has sixteen 32-bit registers, split into data and address registers.

Like many other CPUs of its generation, it can fetch the next instruction during execution (2 stage pipeline).

The 68000 was used in many workstations, notably early Sun-2 machines, and home computers like Apple Macintosh, Commodore Amiga and Atari ST series.

Variants of the 68000 include the 68HC000 (a low-power HCMOS implementation) and the 68008 (an eight-bit data bus version used in the Sinclair QL).

The 68EC000 is a 68000 with selectable 8 or 16 bit data bus and A0.

The 68HC05 (HC05 in short) is a broad family of 8-bit microcontrollers from Freescale Semiconductor (formerly Motorola Semiconductor).

Like all Motorola processors that share lineage from the 6800, they use the von Neumann architecture as well as memory-mapped I/O. This family has five CPU registers that are not part of the memory: an 8-bit accumulator A, an 8-bit index register X, an 8-bit stack pointer SP with two most significant bits hardwired to 1, a 13-bit program counter PC, and an 8-bit condition code register CCR.

Among the HC05s there are several processor families, each targeted to different embedded applications.

The 68HC05 family broke ground with the introduction of the EEPROM-based MC68HC805C4 and MC68HC805B6 variants in the late 1980s. Using a serial bootloader, they could be programmed in-circuit with simple software running on a PC and a low current 19V supply (no programmer required).

PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance (AIM).

Power (Performance Optimization With Enhanced RISC) and was adopted from IBMs POWER architecture from their RS/6000 series.

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:
big or little-endian modes (requiring a reset)
single-precision floating point in addition to double-precision
additional floating point instructions at the behest of Apple
a complete 64-bit specification, which is backward compatible with the 32-bit mode
removal of some of the more esoteric POWER instructions, which are emulated in microcode
The first single-chip implementation of the design was the MCP601 and released in Apples PowerMac in March 1994

The PowerPC 604 was the high end PowerPC when released, performing at 1.5 times the speed of a PowerPC 601 at equal clock speeds.
The chip was later updated by doubling the L1 cache to 64KB and shrinking the processor, now dubbed the 604e.

The fastest versions of the 604e version were nicknamed Mach 5 and ran at 250-350MHz.

Codenamed Arthur, the PowerPC G3 name comes from the third generation of PowerPC microprocessor. It was used in Apple Macintosh computers such as the PowerBook G3, the iMacs, iBooks and several desktops, including the Power Macintosh G3s.

The G3 was introduced in two different versions, derived from the PPC 603 series of microprocessors: the PPC 740 and PPC 750 microprocessors. The PPC 740 slightly outperformed Pentium IIs while consuming less than 20% of the amount of power and size. Derived from the PPC 740, the PPC 750 had a faster way to access L2 cache, which allowed higher performance.

The earlier versions, made by Motorola, used an aluminium process for fabrication, and were limited to 400 MHz speeds. Later versions, manufactured by IBM with a silicon-on-insulator fabrication process, achieved speeds of 500 MHz and beyond. All G3 versions did not completely implement a standard for symmetric multiprocessing computers, which made design and manufacture of a SMP computer comparatively difficult. The PowerPC G4 corrected this deficiency.

With its combination of small size and low power requirements, the G3 proved an ideal laptop microprocessor in its era. Apple ceased using the G3 on October 22, 2003.

The fourth generation of PowerPC processors, the PPC G4, is used in Apple Macintosh computers such as the G4 PowerBook, the 2nd generation Flat Panel iMac, the eMac, the 3rd generation iBook, and the desktop G4 Power Mac.

Most of the G4 design was done by Motorola in close cooperation with Apple. IBM, the third member of the AIM alliance, chose not to participate in the design of the G4 in part owing to microprocessor design disagreements concerning a Vector Processing Unit on the chip. Ultimately, the G4 architecture design contained a 128-bit vector processing unit called AltiVec.

With the AltiVec unit, the G4 microprocessor can do four-way single precision floating point math, or 16-way byte math in a single cycle. Furthermore, the vector processing unit on the G4 is superscalar, and can do two vector operations at the same time. Compared to Intels x86 microprocessors at the time, this feature offered a substantial performance boost, if the application was coded to take advantage of the AltiVec unit.

PowerQUICC Integrated Communications Processor
The MPC860 PowerQUICC is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products.

CPU of 32-bits, developed by Digital Equipment Corporation and installed in the MicroVAX II computers.

The VIA C3 is a family of x86 central processing units for personal computers designed by Centaur Technology and sold by VIA Technologies. The different CPU cores are built following the design methodology of Centaur Technology.

In addition to x86 instructions, VIA C3 CPUs contain an undocumented Alternate Instruction Set allowing lower-level access to the CPU and in some cases privilege escalation.

The VIA C7 is an x86 central processing unit designed by Centaur Technology and sold by VIA Technologies

The C7 delivers a number of improvements to the older VIA C3 cores but is nearly identical to the latest VIA C3 Nehemiah core. The C7 was officially launched in May 2005, although according to market reports, full volume production was not in place at that date.
In May 2006 Intels cross-licensing agreement with VIA expired and was not renewed, which was the reason for the forced termination of C3 shipments on March 31, 2006, as VIA lost rights to the socket 370. The C7 appears still to be found in the marketplace, for example, on the bargain-priced Everex TC2502, sold by Walmart with a Linux distribution preinstalled and on the HP Mini-Note.

Cyrix III is an x86-compatible Socket 370 CPU. VIA Technologies launched the processor in February 2000. VIA had purchased both Centaur Technology and Cyrix. Cyrix III was to be based upon a core from one of the two companies.

The VIA Nano (formerly code-named VIA Isaiah) is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development[1] by its CPU division, Centaur Technology.

Unlike Intel and AMD, VIA uses two distinct development code names for each of its CPU cores. In this case, the codename CN was used in the United States by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W.

ZiLOG is a manufacturer of 8-bit CPUs, and is most famous for its Z80 series. Zilog was incorporated in California in 1974 by Federico Faggin, who left Intel after working on the 8080, and the Z80 shared many features with it.

After the Z80 Zilog introduced 16-bit and 32-bit processors, but these were not particularly successful, and the company refocused on the microcontroller market, producing both basic CPUs and application-specific integrated circuits/standard products (ASICs/ASSPs) built around a CPU core. As well as producing processors, Zilog have produced several other components. One of the most famous was the Z8530 serial communications controller as found on Sun SPARCstations and SPARCservers up to the SPARCstation 20.

The company became a subsidiary of Exxon in 1980, but the management and employees bought it back in 1989. It went public in 1991, but was acquired in 1998 by Texas Pacific Group, who, after chip prices plummeted, reorganized the company in a Chapter 11 bankruptcy in late 2001.

Zilog Z8000 is a family of 16-bit microprocessors introduced in 1979 between the Intel 8086 and the Motorola 68000. The series has been designed by Masatoshi Shima and produced by Zilog and second sources AMD, SGS and Hitachi from 1979 until 1995. Since 1995, the CPU series continues to live and still is in production by Zilog in a pin-compatible CMOS release called the Z16C00 series (with the Z16C01 as the equivalent of Z8001 and the Z16C02 as the equivalent of Z8002). There are 4 slightly different Z8000 versions:
Z8001: large memory version, can address up to 8 MB (divided into 128 segments up to 64 KB each)
Z8002: small memory version, can address 64 KB
Z8003: same as the Z8001 with added virtual memory support
Z8004: same as the Z8002 with added virtual memory support
The Z8000 series introduced a number of attractive new features from the mini-computer and mainframe worlds:
Regular general-purpose register file (16 16-bit registers that could be used as accumulators, address registers, index registers or stackpointers)
Separation of Normal and System modes (also known as User and Supervisor modes) for enhancing system integrity
Large address space (8Mb)
First commercial Memory management facility (Z8010 Z-MMU)
Extended Processing Architecture (EPA) allowing co-processing in an efficient parallel fashion
The Z8000 processor also had some drawbacks as compared to its close rival, the Motorola 68000:
Segmented addressing: maximum segment size of 64Kb which complicates the addressing of very large data structures
Delayed introduction due to tecnical problems
Limited support (very limited software base, limited hardware support)
Although initially the Z8000 got some acceptance and was widely recognised to have a very elegant and user-friendly architecture, it became quickly surpassed by the Motorola 68000 and the Intel 80286 in the commercial domain. In safe-critical environments however the processor apparently continued to play an important role.